it is amazing

on how many chips linux can run https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch

CPUs you probably have NEVER heared of 😀

OpenRISC – Academic and non-commercial use

Being open source, OpenRISC has proved popular in academic and hobbyist circles. For example, Stefan Wallentowitz and his team at the Institute for Integrated Systems at the Technische Universität München have used OpenRISC in research into multicore architectures.[11] The Open Source Hardware User Group in the UK has on two occasions[12][13] run sessions on OpenRISC, while hobbyist Sven-Åke Andersson has written a comprehensive blog on OpenRISC for beginners,[14] which attracted the interest of EE Times.[15] Sebastian Macke has implemented jor1k, an OpenRISC 1000 emulator in JavaScript, running Linux with X Window System and Wayland support.[16]

https://en.wikipedia.org/wiki/OpenRISC

System on Chip

Project Files Statistics Status License
16-core OR1K2 SoC No Stats LGPL
AHB DMA 32 / 64 bits Yes Stats LGPL
AHB DMA 32 bits No Stats LGPL
ahb system generator Yes Stats Done LGPL
AHB to Wishbone Bridge Yes Stats Done Wbc
ALEX No Stats Wbc LGPL
aoOCS – Wishbone Amiga OCS SoC Yes Stats Wbc BSD
Arm core Yes Stats
Assembler with VHDL User-defined Commands (AVUC) Yes Stats Done LGPL
Async-SDM-NoC Yes Stats Done LGPL
AXI DMA 32 / 64 bits Yes Stats LGPL
AXI4 Transactor and Bus Functional Model Yes Stats Done LGPL
CCSDS RX_TX_SoC No Stats Wbc LGPL
CMOD S6 SoC Yes Stats Done Wbc GPL
CPU Lecture Yes Stats GPL
ECO32 Yes Stats BSD
ELA(Embedded Logic Array) No Stats Wbc LGPL
Embedded 32-bit RISC uProcessor with SDRAM Controller Yes Stats
Embedded FPGA Core Yes Stats
EPC RFID Transponder Yes Stats LGPL
Experimental Unstable CPU Yes Stats Done LGPL
GDP64HS FPGA No Stats LGPL
* GECKO3 SoC co-design environment Yes Stats Done Wbc OCCP Others
GECKO4 SoC co-design environment Yes Stats Others
Generic AHB matrix Yes Stats LGPL
Generic APB register file Yes Stats LGPL
Generic AXI DMA No Stats New LGPL
Generic AXI interconnect fabric Yes Stats LGPL
Generic AXI to AHB bridge Yes Stats LGPL
Generic AXI to APB bridge Yes Stats LGPL
I2C Controller Wishbone Wrapper Yes Stats Wbc LGPL
Internal communication bus for FPGA Yes Stats New BSD
IP Core for 32 bit On-Chip Router for Network On Chip No Stats GPL
layer[2] Yes Stats Done GPL
M16C5x Yes Stats Done LGPL
* minsoc Yes Stats Done Wbc OCCP LGPL
minsocv2 No Stats LGPL
Modified Miller Decoder for ISO14443A from 106Kbps to 847Kbps No Stats Others
MP3 decoder Yes Stats
Next186 SoC PC Yes Stats Done LGPL
Next186MP3 Yes Stats LGPL
NoC based MPSoC Yes Stats Wbc LGPL
NoC(Network-on-Chip) Simulator Yes Stats LGPL
NoCem — Network on Chip emulator Yes Stats GPL
NoCmodel Yes Stats LGPL
OC – H.264 Encoder SoC Yes Stats LGPL
OMS8051 MINI Yes Stats LGPL
Open Tiled Multicore SoC No Stats Wbc LGPL
OpenFIRE Yes Stats
OpenSPARC-based SoC Yes Stats GPL
or1200_soc Yes Stats Wbc
Or1k SoC on Altera Embedded Dev Kit Yes Stats Wbc LGPL
ORPSoC No Stats LGPL
PDP-1 reimplementation Yes Stats LGPL
PIF2WB Yes Stats Done Wbc
PLBv46 to Wishbone Bridge Yes Stats Wbc
Project Oberon with SDRAM Yes Stats LGPL
PSS (Programmable Supervisor for Systems-on-Chip) Yes Stats BSD
Real-time image processing Yes Stats LGPL
rfid tag and reader Yes Stats GPL
rtf68kSys Yes Stats Wbc LGPL
SardMIPS Yes Stats GPL
SBA – Simple Bus Architecture No Stats LGPL
SimpCon – a Simple SoC Interconnect Yes Stats LGPL
Simple AXI4-Lite bridges for IPbus and Wishbone Yes Stats Others
Soft MultiProcessor on FPGA Yes Stats GPL
STORM SoC Yes Stats Wbc GPL
System-On-Chip based on bare Rocket-chip (RISC-V ISA) Yes Stats Done BSD
System-on-Chip Wire (SoCWire) Yes Stats Done
system05 Yes Stats GPL
System09 Yes Stats GPL
WB/OPB & OPB/WB Interface Wrapper Yes Stats Wbc
WISHBONE Builder Yes Stats Wbc
WISHBONE Conbus IP Core Yes Stats Wbc
WISHBONE Conmax IP Core Yes Stats Wbc
WISHBONE DMA/Bridge IP Core Yes Stats Wbc
wishbone out port from b3 spec Yes Stats Done Wbc LGPL
Wishbone System6800/01 Yes Stats Done Wbc
Wishbone to AHB Bridge Yes Stats Wbc
Wishbone Transactor and Bus Functional Model No Stats Wbc LGPL
WishboneTK toolkit Yes Stats Wbc
XuLA2-LX25 SoC Yes Stats Wbc GPL
Z80 System on Chip Yes Stats
Zorro bus to Wishbone bridge Yes Stats Wbc LGPL
ZPUino No Stats BSD
ztachip No Stats LGPL

Links:

http://opencores.org/projects

https://openrisc.io/

admin